跪求一个利用VHDL语言设计一个4位向量乘法器的程序是向量乘法器不是乘法器追奖100分

跪求一个利用VHDL语言设计一个4位向量乘法器的程序是向量乘法器不是乘法器追奖100分
跪求一个利用VHDL语言设计一个4位向量乘法器的程序
是向量乘法器不是乘法器
追奖100分

跪求一个利用VHDL语言设计一个4位向量乘法器的程序是向量乘法器不是乘法器追奖100分
library ieee;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY part6 IS
PORT(DATAA,DATAB:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
RESULT:OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
END part6;
architecture BEHAVIOR OF part6 IS
COMPONENT MULTIPLIER_4BIT
PORT(A,B:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
P:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;
SIGNAL SUM12H,SUM12L:STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL SIN3,SIN2,SIN1,SIN0:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
UNIT1:MULTIPLIER_4BIT PORT MAP(A=>DATAA(3 DOWNTO 0),B=>DATAB(3 DOWNTO 0),P=>SIN0);
UNIT2:MULTIPLIER_4BIT PORT MAP(A=>DATAA(7 DOWNTO 4),B=>DATAB(3 DOWNTO 0),P=>SIN1);
UNIT3:MULTIPLIER_4BIT PORT MAP(A=>DATAA(3 DOWNTO 0),B=>DATAB(7 DOWNTO 4),P=>SIN2);
UNIT4:MULTIPLIER_4BIT PORT MAP(A=>DATAA(7 DOWNTO 4),B=>DATAB(7 DOWNTO 4),P=>SIN3);
SUM12L'0',S=>P(1),CO=>C1(0));
FA2:ADDER_1BIT PORT MAP(DA=>A(2) AND B(0),DB=>A(1) AND B(1),CI=>C1(0),S=>S1(0),CO=>C1(1));
FA3:ADDER_1BIT PORT MAP(DA=>A(3) AND B(0),DB=>A(2) AND B(1),CI=>C1(1),S=>S1(1),CO=>C1(2));
FA4:ADDER_1BIT PORT MAP(DA=>'0',DB=>A(3) AND B(1),CI=>C1(2),S=>S1(2),CO=>C1(3));
FA5:ADDER_1BIT PORT MAP(DA=>S1(0),DB=>A(0) AND B(2),CI=>'0',S=>P(2),CO=>C2(0));
FA6:ADDER_1BIT PORT MAP(DA=>S1(1),DB=>A(1) AND B(2),CI=>C2(0),S=>S2(0),CO=>C2(1));
FA7:ADDER_1BIT PORT MAP(DA=>S1(2),DB=>A(2) AND B(2),CI=>C2(1),S=>S2(1),CO=>C2(2));
FA8:ADDER_1BIT PORT MAP(DA=>C1(3),DB=>A(3) AND B(2),CI=>C2(2),S=>S2(2),CO=>C2(3));
FA9:ADDER_1BIT PORT MAP(DA=>S2(0),DB=>A(0) AND B(3),CI=>'0',S=>P(3),CO=>C3(0));
FA10:ADDER_1BIT PORT MAP(DA=>S2(1),DB=>A(1) AND B(3),CI=>C3(0),S=>P(4),CO=>C3(1));
FA11:ADDER_1BIT PORT MAP(DA=>S2(2),DB=>A(2) AND B(3),CI=>C3(1),S=>P(5),CO=>C3(2));
FA12:ADDER_1BIT PORT MAP(DA=>C2(3),DB=>A(3) AND B(3),CI=>C3(2),S=>P(6),CO=>P(7));
P(0)